4. Processor Fundamentals

CPU Architecture

Stored Program Concept

Instructions and data are stored in the same memory space within main memory, allowing for flexible program execution and data manipulation.

Control Unit (CU)

Arithmetic Logic Unit (ALU)

System Clock

Buses

Registers

General Purpose Registers

Hold temporary data during operations
Can be used for any purpose
Available for most instructions

Special Purpose Registers

Program Counter (PC)

Stores next instruction address, increments after execution

Memory Address Register (MAR)

Holds memory address for read/write operations

Memory Data Register (MDR)

Stores data read from or to be written to memory

Current Instruction Register (CIR)

Holds current instruction being decoded/executed

Status Register

Stores flags for arithmetic/logical operations

Fetch-Execute Cycle

Register Notation

A ← [B] : Copy contents of register B to A

A ← [B] + 1 : Increment B and store in A

A ← [[B]] : Set A to data at address in B

Complete Cycle

1. MAR ← [PC]

2. MDR ← [[MAR]]

3. CIR ← [MDR]

4. PC ← [PC] + 1

Performance Factors

Number of Cores

• Multiple instructions per clock pulse
• Parallel processing capability
• Requires multi-threaded software

Clock Speed

• Determines instruction execution rate
• Higher speed = more F-E cycles
• Affects overall performance

Cache Memory

• Fast access to frequent data
• Reduces memory access time
• Prevents CPU idle time

Bus Width

• Determines data transfer capacity
• Wider bus = more parallel data
• Affects system throughput